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Ordering number : ENA0081B
Monolithic Digital IC
LB11873
Overview
For Polygonal Mirror Motors
Three-Phase Brushless Motor Driver
The LB11873 is a 3-phase brushless motor driver developed for driving the polygonal mirror motor used in plain-paper copiers and similar products. This IC can implement the circuits required for polygonal mirror motor drive (speed control and driver circuits) in a single chip. The LB11873 implements low-noise/low-vibration PWM drive by changing the current at phase switching gradually to reduce motor noise.
Functions
* Three-phase bipolar drive (quiet direct PWM) * PLL speed control circuit * Hall sensor FG support * Dedicated external clock * Brake mode switching circuit (free running and reverse braking) * Phase lock detection output (with masking function) * Built-in current limiter, constraint protection, undervoltage protection, thermal protection, and CLK line disconnection protection circuits * Input pins support 3V system microcontrollers
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Symbol VCC max IO max Pd max1 Pd max2 T 500ms Independent IC When mounted on a circuit board *1 Conditions Ratings 30 1.8 0.9 2.1 Unit V A W W
*1 Specified circuit board : 114.3 x 76.1 x 1.6mm3, glass epoxy. Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
71107 TI PC 20070621-S00004/41807 TI PC B8-9144 No.A0081-1/14
LB11873
Continued from preceding page. Parameter Operating temperature Storage temperature Symbol Topr Tstg Conditions Ratings -20 to +80 -55 to +150 Unit C C
Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage range 5V constant voltage output LD pin apply voltage LD pin output current FGS pin apply voltage FGS pin output current HB pin apply voltage HB pin output current Symbol VCC IREG VLD ILD VFGS IFGS VHBS IHBS Conditions Ratings 9.5 to 28 0 to -30 0 to 28 0 to 15 0 to 28 0 to 10 0 to 28 0 to 30 Unit V mA V mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC = VM = 24V
Parameter Supply current 1 Supply current 2 Symbol ICC1 ICC2 Stop mode Conditions min Ratings typ 22 4.0 max 28 6.0 mA mA Unit
5V constant voltage output (VREG pin) Output voltage Line regulation Load regulation Temperature coefficient Output Block Output saturation voltage 1 Output saturation voltage 2 Output leakage current High side diode forward voltage 1 High side diode forward voltage 2 Hall Sensor Amplifier Block Input bias current Differential input range Common-mode input voltage range Input offset voltage Hall Sensor Bias Output saturation voltage Output leakage current FG Schmitt Trigger Block (IN1) Input amplifier gain Input hysteresis (high low) Input hysteresis (low high) Hysteresis PWM Oscillator High-level output voltage Low-level output voltage External capacitor charge current Oscillator frequency Amplitude f (PWM) V (PWM) C = 680pF 1.45 34 1.75 2.05 kHz Vp-p VOH (PWM) VOL (PWM) ICHG VPWM = 2V 2.65 0.9 -60 2.95 1.2 -45 3.25 1.5 -30 V V A GFG VSHL VSLH VFGL Design target value* Design target value* Design target value* Input conversion, design target value * 4 5 0 -10 7 12 Times mV mV mV VOL (HB) IL (HB) IHB = 10mA VO = VCC, stop mode 1.5 2.0 10 V A VIOH Design target value* -20 IHB VIHIN VICM Sine wave input 50 1.5 2 10 350 VREG - 1.0 20 mV V A VD2-2 ID = 1.2A 1.5 2.0 V VOsat1 VOsat2 IOleak VD2-1 ID = 0.5A 1.0 IO = 0.5A, VO (sink) + VO (source) IO = 1.2A, VO (sink) + VO (source) 1.4 2.0 1.9 2.6 100 1.5 V V A V VREG VREG1 VREG2 VREG3 VCC = 9.5 to 28V IO = -5 to -20mA Design target* 4.65 5.0 80 10 0 5.35 130 60 V mV mV mV/C
* The design specification items are design guarantees and are not measured. Continued on next page.
No.A0081-2/14
LB11873
Continued from preceding page. Parameter FGS Pin Output saturation voltage Output leakage current CSD Oscillator Circuit Oscillator frequency High-level output voltage Low-level output voltage Amplitude External capacitor charge current External capacitor discharge current Lock detection delay counts Clock disconnected protection counts Constraint protection operation counts Initial reset voltage Phase Comparator Output High-level input voltage Low-level input voltage Input source current Input sink current Phase Lock Detection Output Output saturation voltage Output leakage current Error Amplifier Block Input offset voltage Input bias current High-level output voltage Low-level output voltage DC bias level Current Llimiter Circuit Drive gain 1 Drive gain 2 Llimiter voltage 1 Llimiter voltage 2 Thermal shutdown circuit Thermal shutdown operating temperature Thermal shutdown temperature hysteresis Low Voltage Protection Circuit Operating voltage Hysteresis CLK pin External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current fI (CLK) VIH (CLK) VIL (CLK) VIO (CLK) VIS (CLK) IIH (CLK) IIL (CLK) VCKIN = VREG VCKIN = 0V -220 0.1 2.0 0 3.0 0.25 115 -175 150 10 VREG 1.0 kHz V V V V A A Continued on next page. Note : * The design specification items are design guarantees and are not measured. VSDL VSD 8.1 0.2 8.45 0.35 8.9 0.5 V V TSD TSD Design target value* (junction temperature) Design target value* (junction temperature) 40 C 150 170 C GDF1 GDF2 VRF1 VRF2 In the phase locked state In the unlocked state VCC - VM, forward mode VCC - VM, reverse mode 0.4 0.8 0.45 0.225 0.5 1.0 0.5 0.25 0.6 1.2 0.55 0.275 Times Times V V VIO (ER) IB (ER) VOH (ER) VOL (ER) VB (ER) IEI = -0.1mA, no load IEI = 0.1mA, no load Design target value* -10 -1 3.7 0.7 -5% 4.0 1.0 VREG/2 10 1 4.3 1.3 5% mV A V V V VOL (LD) IL (LD) ILD = 10mA VO = VCC 0.15 0.5 10 V A VPDH VPDL IPD+ IPDIOH = -100A IOL = 100A VPD = VREG/2 VPD = VREG/2 1.5 VREG - 0.2 VREG - 0.1 0.2 0.3 -0.5 V V mA mA VRES 0.6 0.8 V CSDCT3 31 CSDCT1 CSDCT2 7 2 ICHG2 VCSD = 2V 3 5 7 A f (CSD) VOH (CSD) VOL (CSD) V (CSD) ICHG1 VCSD = 2V C = 0.033F 3.50 1.00 2.20 -7 31 3.75 1.30 2.45 -5 4.00 1.60 2.80 -3 Hz V V Vp-p A VOL (FGS) IL (FGS) IFGS = 7mA VO = VCC 0.15 0.5 10 V A Symbol Conditions min Ratings typ max Unit
No.A0081-3/14
LB11873
Continued from preceding page. Parameter S/S pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current BRSEL pin High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current VIH (BRSEL) VIL (BRSEL) VIO (BRSEL) VIS (BRSEL) IIH (BRSEL) IIL (BRSEL) VBRSEL = VREG VBRSEL = 0V -220 0.21 2.0 0 3.0 0.25 115 -175 0.29 150 VREG 1.0 V V V V A A VIH (SS) VIL (SS) VIO (SS) VIS (SS) IIH (SS) IIL (SS) VS/S = VREG VS/S = 0V -220 0.21 2.0 0 3.0 0.25 115 -175 0.29 150 VREG 1.0 V V V V A A Symbol Conditions min Ratings typ max Unit
Package Dimensions
unit : mm (typ) 3235A
Allowable power dissipation, Pd max - W
17.8 (6.2) 2.7 36
2.5 2.1W 2.0
Pd max - Ta
Specified circuit board : 114.3x76.1x1.6mm3 glass epoxy board
0.65
1.5 1.18W 1.0 0.9W
(4.9)
10.5
7.9
Independent IC
1 (0.5)
(2.25)
0.25 0.8 2.0 0.3
0.5
2.45max
0 - 20
0
20
40
60
80
100
0.1
Ambient temperature, Ta - C
SANYO : HSOP36(375mil)
Three-Phase Logic Truth Table (The input "H" state is the state where IN+ > IN-)
IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
S/S pin
Input state High or open Low State Stop Start
BRESEL pin
Input state High or open Low During deceleration Free running Reverse braking
No.A0081-4/14
LB11873
Pin Assignment
FRAME OUT3 VCC BRSEL GND2 VREG CLK VM TM NC NC NC PH LD 20 17 FGFIL FGS 19 18 CSD FCS S/S 21 16 EO NC NC
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
LB11873
1 OUT2
2 OUT1
3 NC
4 IN3+
5 IN3-
6 IN2+
7 IN2-
8 IN1+
9 FRAME IN1-
10 HB
11 GND1
12 PWM
13 FCP
14 PD
15 EI
Top view
Hall sensor input waveforms and output current waveform
(1) When the Hall sensor input amplitude is small or when the input waveform slope is low
High IN1 IN2 IN3 Source IOUT1 Sink IOUT2 Low
IOUT3
180 drive: Current flows during all periods; there are on off periods (180 drive) (2) When the Hall sensor input amplitude is larger or when the input waveform slope is steep
High IN1 Low IN2 IN3
IOUT1
Source Sink
IOUT2
IOUT3
In this case, periods in which drive is off will occur (the off periods vary depending on the Hall sensor inputs).
No.A0081-5/14
LB11873
Internal Equivalent Circuit Block Diagram and External Reference Circuit
TM
PWM
PD TSD CSD OSC Count PWM OSC VREG
CSD
EI
S/S S/S
+
EO
BRSEL BRSEL COMP LD LD Peak hold PLL VREG CLK CLK Control circuit VREG VCC VCC FGS FG CURR LIM VM FGFIL Filter Rf CONT AMP
FCP
PH
+
+
Hall amplifier HB Driver
OUT1
OUT2
OUT3
IN1+ IN1VREG
IN2+ IN2-
IN3+ IN3-
HB
FCS
GND2
GND1
No.A0081-6/14
LB11873
Pin Functions
Pin No. 2 1 35 Pin OUT1 OUT2 OUT3 Motor drive outputs Description Equivalent Circuit
VCC 300 VM 28
33
GND2
Output block ground
1
28 VM Motor drive output power supply and output current detection Connect a resistor (Rf) between this pin and VCC. The output current will be limited to the value IOUT = VRF/Rf. 8 9 6 7 4 5 IN1+ IN1IN2+ IN2IN3+ IN3Hall sensor inputs "H" is the state where IN+ > IN-, and "L" is the reverse state. It is desirable that the Hall sensor signals have an amplitude greater than 50 mVpp If noise on the Hall sensor signals is a problem, connect capacitors between the IN+ and IN- inputs.
2
35
33 VREG
300 5 7 9
300 4 6 8
10
HB
Hall sensor element bias current This circuit is turned off in stop mode.
VREG
10
11 12
GND1 PWM
Control circuit block ground Sets the PWM oscillator frequency. Connect a capacitor between this pin and ground. A 680pF capacitor sets the oscillator frequency to be about 34kHz.
VREG
200 2k
12
Continued on next page.
No.A0081-7/14
LB11873
Continued from preceding page. Pin No. 13 Pin FCP correction Connect a capacitor (about 0.01F to 0.1F) between this pin and ground. The output duty is determined by comparing the voltage at this pin with the PWM oscillator waveform. Description Current limiter circuit frequency characteristics Equivalent Circuit
VREG
300 13
14
PD
Phase comparator output The phase error is converted to a pulse duty and output from this pin.
VREG
300 14
15
EI
Error amplifier input
VREG
300 15
16
EO
Error amplifier output
VREG
16 40k
17
FGFIL
FG filter This pin is normally left open. If noise on the FG signal is a problem, connect a capacitor (about 20pF or smaller) between this pin and ground.
VREG
300 17
Continued on next page.
No.A0081-8/14
LB11873
Continued from preceding page. Pin No. 18 Pin CSD reference oscillator Connect a capacitor between this pin and ground. Description Initial reset pulse generation and protection circuit Equivalent Circuit
VREG
300 18
19
FGS
FG Schmitt trigger output
VREG
19
20
LD
Phase lock detection output This output goes to the on state (low-level output) in the phase locked state.
VREG
20
21
S/S
Start/stop control Low : 0V to 1.0V High : 2.0V to VREG Hysteresis : about 0.25V This pin goes to the high level when open. A low level specifies the start state.
VREG
20k 5k 21 30k
22
CLK
Clock input Low : 0V to 1.0V High : 2.0V to VREG Hysteresis : about 0.25V fCLK = 10kHz max. If there is noise on this signal, insert a noise rejection capacitor at this input.
VREG
20k 5k 22 30k
Continued on next page.
No.A0081-9/14
LB11873
Continued from preceding page. Pin No. 23 Pin BRSEL Low : 0V to 1.0V High : 2.0V to VREG This pin goes to the high level when open. A low level selects reverse torque control and a high level selects free running braking. If reverse torque control is used, an external Schottky barrier diode will be required on the low side of the output. Description Deceleration (braking) control selection Equivalent Circuit
VREG
20k 5k 23 30k
24
PH
RF waveform smooth Connect a capacitor between this pin and ground.
VREG
500
34
25
FCS
Control loop frequency characteristics correction Connect a capacitor between this pin and ground.
VREG
300 25
26
TM
Monitor output This pin is normally left open.
VREG
300 26
Continued on next page.
No.A0081-10/14
LB11873
Continued from preceding page. Pin No. 27 Pin VREG Description Stabilized power supply output (5V output) Connect a capacitor between this pin and ground for power supply stabilization. (About 0.1F) Equivalent Circuit
VCC
27
29
VCC
Power supply. Connect a capacitor (a few tens of F or larger) between this pin and ground so that noise does not enter the IC.
3, 30 31, 32 34, 36
NC
Since this pin is not connected internally to the chip, it can be used for wiring connections.
FRAME
Connect this pin to ground.
LB11873 Overview
1. Speed control circuit Since the LB11873 adopts PLL speed control, it provides precise, low-jitter, and stable motor operation. This PLL circuit compares the falling edge of the CLK signal with the FG signal (edges on which the IN1 input changes from low to high and FGS output rising edges) and controls motor operation based on the difference. During control operation, the FG servo frequency is the same as the CLK signal frequency. fFG (servo) = fCLK 2. Output drive circuit This IC minimizes motor vibration and noise by changing the output current smoothly during phase switching. Since the change (slope) imposed on the output current during phase switching uses the slope of the Hall sensor input waveform, the changes in the output waveforms at phase switching will become too steep if the Hall sensor input waveform slope is steep. This will reduce the noise and vibration reducing effect of this technique. Thus care is required concerning the slope of the Hall sensor input waveform. Low side output transistor PWM switching is used for motor speed control and the drive output is adjusted by changing the duty. The diode between OUT and VM used for the regenerative current when the PWM is off is built into this IC. Due to the parasitic diode between OUT and ground, if reverse control mode (torque braking) is selected for braking, an external Schottky barrier diode must be used. Also, if there are problems when the output current is large (for example, incorrect operation or waveform disruption during low side kickback) a Schottky barrier diode must be connected between OUT and ground. Note that if it is necessary to reduce IC thermal dissipation during constant-speed operation, it may be effective to insert a Schottky barrier diode between OUT and VM. This effect occurs because the regenerative current during PWM switching will be dissipated in the external diode instead of the IC's internal diode. 3. Current limiter circuit The current limiter circuit limits the drive current to a current determined by the equation I = VRF/RF, where VRF = 0.5V (typical) and Rf is the current detection resistor. The limiting operation works by reducing other output on duty to suppress the drive current. The current limiter circuit detects the reverse recovery current due to PWM operation and, to assure that the current limiting operation is not performed incorrectly, provides a delay of about 2s before it operates. Since the changes in the current levels at startup (the state where there is no counterelectromotive force from the motor) will be rapid if either the motor coil resistance is low or if the inductance is low, there are cases where current limiter will operates at a current level above that set due to this delay. In these cases, it will be necessary to take the amount of current increase due to the delay into account when setting the current limit value.
No.A0081-11/14
LB11873
4. Power saving circuit This IC goes into a power saving state in which current drain is reduced when set to the stop state. This power saving state is implemented by cutting the bias current to most of the circuits in the IC. The 5V regulator output, however, is still output when the IC is in the power saving state. 5. Reference clock Care must be taken to assure that no noise due to chattering or other problems appears on the externally input clock signal. While the input circuit is designed with hysteresis, noise must be rejected by, for example, inserting capacitors in the clock line if noise problems occur. The LB11873 provides a built-in clock disconnection protection circuit. At clock frequencies lower than the frequency determined by the following equation, the LB11873 will not perform its normal control operation, but rather will operate in an intermittent mode. f (Hz) 1.02 / CCSD CCSD (F) : the capacitor connected between the CSD pin and ground. If a 0.033F capacitor is used, the frequency will be about 31Hz. If the IC is set to the start state with absolutely no clock signal provided, the motor will first start to turn somewhat and then the drive will be turned off. If motor rotation stops, a time in excess of the constraint protection operating time elapses, and then the clock signal is applied again, drive operation will not be restarted. However, if the clock signal is reapplied before the constraint protection circuit operates, drive operation will restart. 6. PWM frequency The PWM frequency is determined by the capacitance of the capacitor (C) connected to the PWM pin. fPWM 1/(43000 x C) If a 680pF capacitor is used, the circuit will oscillate at about 34kHz. If the PWM frequency is too low the motor will emit switching noise, and if it is too high the power loss in the output will increase. A frequency in the range 15kHz to 50kHz is desirable. This capacitor must be connected between this pin and the GND pin by lines that are as short as possible to make this circuit immune to noise. The capacitor ground side must be connected as close as possible to the IC control block ground (the GND1 pin), to minimize the influence of the output. 7. Hall sensor input signals The Hall sensor input signals must have an amplitude (differential) of over 50mVpp. If disruption of the output waveforms occurs due to noise on these signals, capacitors must be connected between the Hall sensor inputs (between the + and - sides). 8. FCS pin The capacitor (about 0.1F) connected to the FC pin is required for correction of the control loop frequency characteristics. 9. Constraint protection circuit The LB11873 includes a built-in constraint protection circuit to protect the IC and the motor if the motor is physically constrained from turning. If FG signal (one side edge of IN1) does not switch states for a period in excess of a certain fixed time in the start state, the PWM drive side output is turned off. The time is set by the capacitor connected to the CSD pin. Set time (seconds) 30.5 x 0.98 x CCSD (F) If a 0.033F capacitor is used, the protection operation time will be about 0.99 seconds. The constraint protection state can be cleared by either switching to the stop state (and remaining for over 100s) or turning the power off and then on again. Note that the constraint protection circuit may not operate correctly if there is noise on the FG signal when the motor is physically constrained.
No.A0081-12/14
LB11873
10. Phase lock signal (1) Phase lock range Since this IC does not have a speed system counter, the speed error range in the phase locked state cannot be determined by the IC characteristics alone. (This is because the range is affected by the acceleration with changes in the FG frequency.) If it is necessary to stipulate this in conjunction with a motor, it will be necessary to measure the range with the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the lock pull-in time at startup and the unlock time due to clock switching will be the cases where the speed error is the largest. (2) Phase lock signal mask function It is possible to assure that the lock signal is output in stable states by masking the short-term low levels due to hunting during lock pull-in. Note, however, that the lock signal output will be delayed by the amount of the mask time. The mask time is set by the capacitor connected between the CLD pin and ground. Mask time (s) 6.5 x 0.98 x CCSD (F) When a 0.033F capacitor is used, the mask time will be about 210ms. If full masking is required, the mask time must be set with an adequate margin. 11. Initial reset To apply an initial reset to the logic circuit, the IC goes to the reset state until the CSD pin voltage changes from 0V to about 0.63V. After the reset is cleared, drive will start. The reset time can be calculated quite closely with the following equation. Reset time (s) 0.13 x CCSD (F) A reset time of over 100s is required. 12. Power supply stabilization Since this IC is used in switching drive applications with large output currents, the power supply line is easily disrupted. Therefore it is necessary to connect an adequately large capacitor between the VCC pin and ground. The capacitor ground side is connected to the GND2 pin, which is the power system ground, and must be connected as close as possible to the pin. If the capacitor (an electrolytic capacitor) cannot be connected close to the pin, a ceramic capacitor of about 0.1F must be connected close to the pin. If reverse control mode (torque braking) is selected for braking, since there will be states where the current returns to the power supply, the power supply line level will be especially subject to disruption. Since the power supply line is most easily disrupted during lock pull-in at high speeds, designers must analyze this case carefully and select an adequately large capacitor. Since the power supply line is particularly susceptible to disruption if a diode is inserted in the power supply line to prevent destruction of the IC by reverse connection, an even larger capacitor must be selected in this case. 13. VREG stabilization Connect a capacitor with a value over 0.1F to stabilize the VREG voltage, which is the IC's control circuit power supply. This capacitor's ground side must be connected as close as possible to the IC's control block ground (the GND1 pin). 14. Error amplifier system components The external components for the error amplifier block must be located as close as possible to the IC to minimize the influence of noise. These components must also be located as far from the motor as possible. 15. FRAME pin An electrolytic capacitor must be connected between the FRAME pin and GND2 with the capacitor's ground side is connected to GND2.
No.A0081-13/14
LB11873
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This catalog provides information as of July, 2007. Specifications and information herein are subject to change without notice. PS No.A0081-14/14

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